1. Field of the Invention
The present invention relates to a programmable logic device which is referred to as PLD hereinafter.
2. Description of the Related Art
A PLD comprises AND circuits and OR circuits combined together to constitute various kinds of logic circuits.
The PLD of prior art has a relatively large dead space due to the structure thereof so that the mount for the circuit is no efficiently used for the chip layout arrangement.
Also, in the process for producing the PLD of the prior art, when the produced PLD is to be tested after sealing with plastic, the signal path at the time of testing is different from that at the time of actual use of the PLD. As a result, though it is possible to detect a defective memory cell on the basis of the difference of the relative delay time, it is difficult to detect the speed of the device at the time of actual use.